p p jl94 3 6 july 10 ,201 5 - rev.00 page 1 6 0 v n - c ha nnel enhancement mode mosfet voltage 6 0 v current 12 a sop - 8 f eatures ? r ds(on) , v gs @10v,i d @ 12 a< 10 m ? high switching speed ? improved dv/dt capability ? low reverse transfer capacitance ? lead free in compliance with eu rohs 2011/65/eu directive. ? green molding compound as per iec61249 std. (halogen free) mechanical data ? case: sop - 8 package ? terminals: solderable per mil - std - 750, method 2026 ? approx. weight: 0.0029 ounces, 0.083 grams ? marking: l 94 36 ma ximum ratings and thermal characteristics (t a =25 o c unless otherwise noted) parameter symbol limit units drain - source voltage v ds 6 0 v gate - source voltage v gs + 20 v continuous drain current t a =25 o c i d 12 a t a = 70 o c 9.5 pulsed drain current (note 1 ) i dm 48 a power dissipation t a =25 o c p d 2.5 w t a = 70 o c 1.6 single pulse avalanche energy (note 5 ) e as 45 mj operatin g junction an d storage temperature range t j ,t stg - 55~150 o c typical thermal resistance - j unction to ambient , t Q (note 6 ) r ja 50 o c /w
p p jl94 3 6 july 10 ,201 5 - rev.00 page 2 e lectrical c haracteristics (t a =25 o c unless otherwise noted) parameter symbol test condition min. typ. max. units static drain - source breakdown voltage bv dss v gs =0v,i d =250ua 6 0 - - v gate threshold voltage v gs(th) v ds =v gs ,i d =250ua 2 .0 2.8 3 .5 v drain - source on - state resistance r ds(on) v gs =10v,i d = 12 a - 8. 5 10 m dss v ds = 48 v,v gs =0v - - 1 .0 u a gate - source leakage current i gss v gs = + 2 0v,v ds =0v - - + 100 n a dynamic (note 7 ) total gate charge q g v ds = 48 v, i d = 12 a, v gs = 10 v (note 1,2 ) - 52 - nc gate - source charge q gs - 11 - gate - dra in charge q gd - 15 - input capacitance ciss v ds = 25 v, v gs =0v, f=1.0mhz - 2904 - pf output capacitance coss - 241 - reverse transfer capacitance crss - 112 - turn - on delay time t d (on) v dd = 30 v, i d =12 a, v g s = 10 v, r g = 6 (note 1,2 ) - 18 - ns turn - on ri se time tr - 48 - turn - o ff delay time t d (off) - 54 - turn - o ff fall time tf - 18 - drain - source diode maximum continuous drain - source diode forward current i s --- - - 12 a diode forward voltage v sd i s = 1 . 0 a, v gs = 0 v - 0. 7 1. 2 v notes : 1. pulse wid th < 300us, duty cycle < 2% 2. essentially independent of operating temperature typical characteristics . 3. the maximum current rating is package limited. 4. repetitive rating, pulse width limited by junction temperature tj(max)=150c. ratings are based on low frequenc y and duty cycles to keep initial tj =25c. 5. the test condition is l=0.1mh, i as = 30 a , v dd =25 v, v gs =10v 6. r ? ja is the sum of the junction - to - case and case - to - ambient thermal resistance where the case thermal reference is defined as the solder mounting surface o f the drain pins. mounted on a 1 inch 2 with 2oz. square pad of copper . 7. guaranteed by design, not subject to production testing.
p p jl94 3 6 july 10 ,201 5 - rev.00 page 3 t ypical characteristic curves fig.1 on - region characteristics fig. 2 transfer characteristics fig. 3 on - resi stance vs. drain current fig. 4 on - resistance vs. junction temperature fig. 5 on - resistance variation with vgs. fig. 6 body d i ode characteristics
p p jl94 3 6 july 10 ,201 5 - rev.00 page 4 t ypical characteristic curves fig. 7 gate - charge characteristics fig. 8 breakdown vo ltage variation vs. temperature fig. 9 threshold voltage variation with temperature . fig. 10 capacitance vs. drain - source voltage . fig. 11 maximum safe operating area
p p jl94 3 6 july 10 ,201 5 - rev.00 page 5 t ypical characteristic curves fig. 12 normalized transient therm al impedance vs. pulse width
p p jl94 3 6 july 10 ,201 5 - rev.00 page 6 p art n o packing code v ersion packaging info rmation & mounting pad layout sop - 8 dimension u nit: mm sop - 8 pad latout u nit: mm p art n o packing c ode package type packing type marking ver sion pj l94 36 _r2 _00001 sop - 8 2.5 k pcs / 13
p p jl94 3 6 july 10 ,201 5 - rev.00 page 7 disclaimer
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